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Implementing Fast Packet Filters by Software Pipelining on x86 Processors
著者
  Yoshiyuki Yamashita, Masato Tsuru
 
雑誌名/会議名
  Proc. 8th APPT, LNCS 5737:420-435. (Aug 2009) 2009 年 8 月
 
アブストラクト
  Packet filters are essential for network traffic/security management on the Internet. Filters implemented by software on general purpose CPUs are very flexible but occasionally suffer from poor performance. In order to address this problem, we have investigated software pipelining techniques for loops with a number of conditional branches for use in software-based fast packet filters. Based on our previous researches, we herein apply the software pipelining approach in an attempt to increase the filter performance for large filter rules. We validate the effectiveness of the proposed approach on Intel x86-32/64 series, as well as Intel Itanium 2 processors, which speaks to the generality and practicality of the proposed approach. The software pipelined program codes on x86-64 processors are 2.2 times faster than C-compiler-based codes and 1.8 times faster than carefully optimized hand-compiled codes. In addition, the performance of the pipelined codes we obtained on x86-64 processors is comparable to that on Itanium 2 processors with predicate registers.
 
キーワード
  Measurement
 
記述言語
  English
 
 

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